1. Field of Invention
This invention relates generally to content addressable memories and specifically to improving the performance of content addressable memories.
2. Description of Related Art
Content addressable memories (CAM) are frequently used for Internet address searching. A conventional CAM 1 having n-bit words is shown in FIG. 1 to include a row of n CAM cells 10 coupled to an associated word line WL. Each CAM cell 10 includes a latch, formed by CMOS inverters 12 and 14, for storing a bit of data. Opposite sides of the latch are coupled to associated complementary bit lines BL and BL via pass transistors 16 and 18, respectively, where each transistor has a gate coupled to the associated word line WL. The output terminal of the inverter 12 is coupled to the gate of an NMOS pass transistor 20, and the output terminal of the inverter 14 is coupled to the gate of an NMOS transistor 22. The transistor 20 is coupled between the associated bit line BL and the gate of an NMOS pull-down transistor 24, and the transistor 22 is coupled between the associated complementary bit line BL and the gate of the pull-down transistor 24. The pull-down transistor 24 is coupled between ground potential and a match line ML associated with the CAM word formed by the cells 10 shown in FIG. 1. A PMOS pull-up transistor 26 is coupled between a supply voltage V.sub.DD and the match line ML.
The pull-up transistor has a gate tied to ground potential and, therefore, remains in a conductive state. A conventional buffer 28 is coupled in series between the match line and an associated sensing circuit (not shown for simplicity).
During compare operations, the word line WL associated with the CAM word shown in FIG. 1 is grounded to turn off the pass transistors 16 and 18 associated with each CAM cell 10. Comparand bits C to be compared with the data bits Q stored in the CAM cells 10 are provided to the associated bit lines BL, and the respective complements of the comparand bit, herein denoted as c, are provided to the associated complementary bit lines BL. For each CAM cell 10, if the comparand bit C matches the data bit Q stored therein, the gate of the corresponding pull-down transistor 24 is driven with a logic low signal via transistors 20 or 22, thereby maintaining the pull-down transistor 24 in a non-conductive state. If, on the other hand, the comparand bit C does not match the data bit Q stored in the CAM cell 10, the gate of the corresponding pull-down transistor 24 is driven with a logic high signal via transistors 20 or 22, thereby turning on the pull-down transistor 24. When conductive, the pull-down transistors 24 pull the match line to ground potential.
Thus, if any of the comparand bits C do not match their corresponding data bits Q stored in the CAM cells 10, the match line ML will be pulled to a logic low state, i.e., ground potential. Conversely, if all of the comparand bits C match their corresponding data bits Q, the match line ML remains at the supply voltage V.sub.DD, i.e., a logic high state. In response to the voltage level on the match line ML, the buffer 28 provides to an associated sense circuit (not shown for simplicity) an output signal indicative of whether all bits of the comparand word match all corresponding bits of the CAM word.
As mentioned above, if there is a mismatch between associated comparand C and data Q bits, the corresponding pull-down transistors 24 turn on and pull the match line ML to ground potential. When this mismatch condition occurs, both the PMOS pull-up transistor 26 and one or more of the pull-down transistors 24 are conductive, thereby forming a path from the supply voltage V.sub.DD to ground potential. This path to ground potential results in significant power dissipation. Further, this undesirable power dissipation increases as the size and/or density of the CAM 1 increases and, therefore, undesirably limits the memory size and the scalability of the CAM 1. Further, since the PMOS transistor 26 is necessarily a weak pull-up transistor so as to allow one or more of the pull-down transistors 24 to pull the match line ML to ground potential in response to a mismatch condition, the pull-up transistor 26 is slow in charging the match line ML to the supply voltage V.sub.DD between compare operations. This slow charging of the match line ML undesirably limits the speed of the CAM 1. Note that increasing the current-carrying capacity of the PMOS pull-up transistor 26 to increase the speed of the CAM 1 may prevent one of the NMOS pull-down transistors 24 from pulling the match line ML to ground potential and thereby results in erroneous match conditions. Further, the conducting pull-up transistor 26 works against the pull-down transistors 24 when discharging the match line ML and, therefore, undesirably slows CAM speed.